The present invention relates generally to signal driving buffer circuits, and more particularly to a set of buffer circuits that increase the speed of signal propagation across heavily loaded lines by early detection of signal transitions.
Buffer circuits are typically utilized either at a signal source, or at the receiving end (i.e. input to a circuit). When a buffer circuit is used at an input to a circuit, the main purpose of buffering is to reshape the falling and rising edges of the signal. An input signal having sharper edges increases the response time of the receiving circuit. However, the signal propagation time through the line is not affected. When a buffer circuit is used at a signal source, it acts as an output driver enabling the source to drive the resistive/capacitive (R/C) loading due to line parasitics and load devices. To be able to drive larger loads, stronger buffer circuits are required which translates to larger transistor sizes. Thus, when an output signal leaves an integrated circuit chip to drive external circuitry, large output buffer circuits are required to drive the increased loading.
The overall chip size requirements often place a limit on how large output buffer transistors can be. The buffer circuit size becomes especially critical when there are a large number of very long connector lines inside a chip that require buffer circuits. An example of such a chip can be found in high density programmable logic devices. These devices typically contain a large number of connector buses (or global lines) that must travel long distances across the chip. In these types of chips, size considerations force the designer to compromise signal propagation speed.
From the foregoing it can be appreciated that there is a need for an improved signal buffer circuit that can increase the speed of signal propagation through heavily loaded lines without requiring unacceptably large silicon area.